sequential circuit造句
例句与造句
- Verification of sequential circuit design based on obdd
时序电路设计的验证 - Asynchronous transmission sequential circuit
传送信号减衰 - Asynchronous sequential circuit
异步时序电路 - Autonomous sequential circuit
自激时序电路 - We also develop a new word - level fault parallel fs algorithin for synchronous sequential circuits
接着又开发了一个新的单机字级故障并行fs算法。 - It's difficult to find sequential circuit in a sentence. 用sequential circuit造句挺难的
- The content of this thesis just is parallel atpg algorithlms and it prototype system for non - scan synchionous sequential circuits
本文的研究内容正是面向非扫描同步时序电路的并行atpg算法。 - Most of vlsi circuits are sequential circuits . sequential circuits can be simulated by symbolic finite state machine ( fsm )
Vlsi系统中大部分是时序电路，时序电路可以用符号化的有限状态机( finite - state - machine ，简称fsm )来模拟。 - Although some scholars have done lots of work on the test generation of the digital circuits , it is still a well - known puzzle to test sequential circuits
虽然各国学者在数字电路测试生成上已做了大量的工作，时序电路的测试生成仍然是公认的难题。 - The sy - stem had different requirements on time sequence in high - speed clock and low - speed clock situations , which resulted in the complexity of the sequential circuit
在高速时钟和低速时钟的情况下，系统有不同的时序要求，这就决定了时序电路的复杂性。 - The international standard sequential circuits iscas ' 89 ( addendum ' 93 included ) is used to verify the algorithm , and the results are better than other algorithms "
采用国际标准时序电路iscas ’ 89 (包括addendum ’ 93 )进行了算法验证，取得了优于文献中其它算法的结果。 - Optimize synchronous sequential circuit with retiming was introduced by leiserson and saxe in 1983 , and retiming optimizational algorithm was summarized comprehensively in 1991
Leiserson和saxe于1983年提出了利用重定时优化同步时序电路，并于1991年对重定时优化算法做了全面的总结。 - The automatic test vector generation method based on fault simulation is described , and the whole procedure of atpg of sequential circuits is analyzed , fault simulator - hope as an example
本文阐述了基于模拟的自动测试生成方法，以故障模拟器? hope为例分析了整个时序电路自动测试生成过程。 - In order to eliminate the sequence conflict of synchronous sequential circuit and shorten the designable time of integrated circuits , the algorithms of retiming is deeply researched in this paper
本文对重定时算法进行了深入研究，目的在于消除同步时序电路的时序冲突，从而缩短集成电路的设计时间。 - To avoid the idleness state and the corresponding power dissipation in sequential circuits , a clock gating technique and a multi - code assignment using redundant state is adanced to reduce power dissipation
为抑制时序电路中的冗余现象，研究了时序电路的门控时钟技术，并利用t型触发器进行时序电路设计。 - Base on the existing synchronous sequential circuits fault simulator - hope , the test vector generation method of sequential circuits based on ant algorithm is systematically researched firstly
本文在同步时序电路故障模拟器? hope的基础上，率先对基于蚂蚁算法的时序电路测试矢量生成方法作了系统的开拓性研究。
更多例句： 下一页